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1394 Trade Association Power Specification, Part 2: Suspend/Resume Implementation Guidelines1999001-Part2 This specification provides informative data pertaining, specifically, to the implementation and application of 1394 suspend/resume mechanisms (as defined in High Speed Serial Bus Specification IEEE 1394a. Portions of that standard have been incorporated into this specification. In instances where this specification is in conflict with IEEE 1394a, the IEEE document shall be the governing standard. The implementation and guidelines suggested within this specification are representations of possible usage models and should be considered when implementing 1394a compliant silicon in a system where power conservation is of paramount concern. Information contained in this specification should not be interpreted as a definitive source of all possible usage models. The incorporation of suspend/resume using 1394a mechanisms may vary for specific platform implementations. The link (host controller) must also support low power mechanisms. However, this specification will not address any low power implementations of the link device (e.g. this specification will address low power management from the PHY perspective only). The low power mechanisms describe in this specification deal with how a port is placed into a low power suspend state in either a port to port connection or on a bus wide basis. How a port resumes is also discussed. In addition, the effect of using the low power mechanisms has on the various portions of the PHY (e.g. the PHY/Link interface, the PHY port interface, and the PHY core) will be discussed. Finally, methods of facilitating notification of various port events will be presented. This document does not discuss the protocol or process by which a node gains power state control of a port, a set of ports in a node, or a set of nodes. Granting and denying a node ownership of power state control for a port, a set of ports, or a set of nodes is discussed in the 1394 Trade Association Power Specification, Part 3: Power State Management.
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